The Erlangen Slot Machine - An FPGA-Based Partially Reconfigurable Computer

Partial recon guration is a special case of device con guration that allows to change only parts of a hardware circuit at run-time. Only a prede ned region of an FPGA is updated while the remainder of the device continues to operate undisturbed. This is especially valuable when a device operates in a missioncritical environment and cannot be disrupted while a subsystem is rede ned for performance or exibility reasons. The triggering of partial recon guration can be instigated by user requests, detected changes of environmental factors or operating system scheduling. It o ers a novel possibility to dynamically load and execute hardware modules, previously only known for software modules. Partial recon guration is useful in increasing the computational exibility and e ciency by time-sharing the existing memory and logic resources on the device. Using partial recon guration, the functionality of a single FPGA is increased, allowing fewer or smaller FPGA devices to be used. Embedded systems using FPGAs supporting partial recon guration can be customized in their hardware at run-time with partial recon guration. However, the design ow and peripheral I/O architectures of these devices are not ideally suited for run-time recon gurable application development. Therefore, the bene ts of partial recon guration used in hardware designs are currently seen as limited. The Erlangen Slot Machine (ESM) is introduced as a new FPGA-based dynamically recon gurable computer architecture supporting run-time customization through the use of partial recon guration at its architectural level. Built within the DFG priority program 1148 Recon gurable Computing its main goals are: • making partial recon gurable designs viable for real-world applications,